1. Field of the Invention
The invention relates to the field of translation tools and more particularly to tools for translating imperative-language functions into hardware description language.
2. Description of the Related Art
Considerable interest exists for tools that translate functions written in an imperative programming language (e.g., C++, C, Java, MATLAB) into a component that can be implemented as hardware. Xilinx of San Jose, Calif. has a System Generator toolset that includes a tool that will translate certain functions written in the MATLAB language (an imperative, scripting language) into a synthesizable hardware description language (HDL) such as synthesizable VHDL or Verilog. Other companies such as AccelChip are developing similar and competing capabilities. AccelChip, for example, develops MATLAB language to hardware toolsets.
Translating a function written in an imperative language into a hardware component that has multiple inputs and multiple outputs is desirable. Fortunately, the MATLAB programming language has the desirable property of enabling a function to return multiple values, for example:
function[sum, diff]=addsub (a, b)                sum=a+b;        diff=a−b;        
return;
The code above defines a function, “addsub,” that returns two values, “sum” and “diff.” Such a function is intuitively translated into a hardware component with two input ports (a, b) and two output ports (sum, diff). In this manner the imperative language has a function declaration syntax easily mapped into a component declaration in a Hardware Description Language (HDL). For example, the HDL equivalent of the MATLAB code above would appear as follows:
component addsub                port (                    a: in std_logic vector (15 downto 0);            b: in std_logic_vector (15 downto 0);            sum: out std_logic_vector (15 downto 0);            diff: out std_logic_vector (15 downto 0)                        );        
end component;
Besides the function itself, it is also desirable to parameterize a hardware component so that it can implement a range of functionality, or so that it can use a range of architectural implementations. For example, it could be useful to create an addsub component that has two inputs (a, b) and one output (s), that can be parameterized such that each addsub instance either computes s=a+b or s=a−b. Traditional HDLs provide mechanisms (generics in VHDL, parameters in Verilog) by which components can be parameterized in this way. A parameterizable addsub component might be declared in VHDL using generics as follows:
component addsub                generic (                    compute_sum: boolean—if true, compute a+b, else compute a−b                        );        port (        a: in std_logic_vector (15 downto 0);        b: in std_logic_vector (15 downto 0);        s: out std_logic_vector (15 downto 0)        
);
end component;
In translating imperative-language function definitions into hardware components, it would be useful to provide a similar component parameterization scheme. Most imperative languages do not have a syntax for a parameterized collection of functions. C++ is an exception with its function templating mechanisms as illustrated below:                template <bool compute_sum> int addsub (int a, int, b)        {                    int s;                        if (compute_sum) s=a+b;                    else s=a−b;            return s;                        }        
Even with this mechanism, the proposition of translating templated, imperative functions into parameterized, hardware components is not very practical or attractive.